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| MC100EP809 3.3V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable Description http://onsemi.com MARKING DIAGRAM* The MC100EP809 is a low skew 1-to-9 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. The two clock inputs are differential HSTL or PECL and they are selected by the CLK_SEL pin which is LVTTL. To avoid generation of a runt clock pulse when the device is enabled/disabled, the Output Enable (OE), which is LVTTL, is synchronous ensuring the outputs will only be enabled/disabled when they are already in LOW state (Figure 8). The MC100EP809 guarantees low output-to-output skew. The optimal design, layout, and processing minimize skew within a device and from lot to lot. The MC100EP809 output structure uses open emitter architecture and will be terminated with 50 W to ground instead of a standard HSTL configuration (Figure 6). To ensure the tight skew specification is realized, both sides of the differential output need to be terminated identically into 50 W even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. Designers can take advantage of the EP809's performance to distribute low skew clocks across the backplane of the board. HSTL clock inputs may be driven single-end by biasing the non-driven pin in an input pair (Figure 7). Features MC100 EP809 32-LEAD LQFP FA SUFFIX CASE 873A AWLYYWWG 32 1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. * 100 ps Typical Device-to-Device Skew * 15 ps Typical within Device Skew * HSTL Compatible Outputs Drive 50 W to GND with no * * * * * * Offset Voltage Maximum Frequency > 750 MHz 850 ps Typical Propagation Delay Fully Compatible with Micrel SY89809L PECL and HSTL Mode Operating Range: VCCI = 3 V to 3.6 V with GND = 0 V, VCCO = 1.6 V to 2.0 V Open Input Default State Pb-Free Packages are Available (c) Semiconductor Components Industries, LLC, 2006 November, 2006 - Rev. 7 1 Publication Order Number: MC100EP809/D MC100EP809 VCCO VCCO 17 16 15 14 VCCO Q6 Q6 Q7 Q7 Q8 Q8 VCCO 13 12 11 10 9 1 2 3 4 5 6 7 8 OE CLK_SEL L H L H Q3 Q3 Q4 Q4 Q5 19 LVPECL_CLK Q5 18 GND 24 VCCO Q2 Q2 Q1 Q1 Q0 Q0 VCCO 25 26 27 28 29 30 31 32 23 22 21 20 MC100EP809 VCCI HSTL_CLK HSTL_CLK CLK_SEL All VCCI, VCCO, and GND pins must be externally connected to appropriate Power Supply to guarantee proper operation (VCCI 0 VCCO). Figure 1. 32-Lead LQFP Pinout (Top View) Table 1. PIN DESCRIPTION PIN HSTL_CLK*, HSTL_CLK** LVPECL_CLK*, LVPECL_CLK** CLK_SEL** OE** Q0 - Q8, Q0 - Q8 VCC1 VCC0 GND FUNCTION HSTL or LVDS Differential Inputs LVPECL Differential Inputs LVCMOS/LVTTL Input CLK Select LVCMOS/LVTTL Output Enable HSTL Differential Outputs Positive Supply_Core (3.0 V - 3.6 V) Positive Supply_HSTL Outputs (1.6 V - 2.0 V) Ground LVPECL_CLK Table 2. TRUTH TABLE OE* L L H H Q0 - Q8 L L HSTL_CLK LVPECL_CLK Q0 - Q8 H H HSTL_CLK LVPECL_CLK *The OE (Output Enable) signal is synchronized with the rising edge of the HSTL_CLK and LVOCL_CLK signals. * Pins will default LOW when left open. ** Pins will default HIGH when left open. http://onsemi.com 2 MC100EP809 CLK_SEL HSTL_CLK HSTL_CLK LVPECL_CLK VCCI GND LVPECL_CLK OE D 0 9 9 1 Q VCCO Q0-Q8 (HSTL) Q0-Q8 (HSTL) Figure 2. Logic Diagram Table 3. ATTRIBUTES Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Pb Pkg Level 2 Value 75 kW 37.5 kW > 2 kV > 200 V > 2 kV Pb-Free Pkg Level 2 Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) LQFP-32 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in 478 Devices http://onsemi.com 3 MC100EP809 Table 4. MAXIMUM RATINGS Symbol VCC1 VCC0 VI Iout TA Tstg qJA qJC Tsol Parameter Core Power Supply HSTL OutputPower Supply PECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board LQFP-32 LQFP-32 LQFP-32 Condition 1 GND = 0 V GND = 0 V GND = 0 V Continuous Surge Condition 2 VCC1 = 1.8 V VCC0 = 3.3 V VI v VCC1 Rating 4 4 6 50 100 0 to +85 -65 to +150 80 55 12 to 17 265 265 Unit V V V mA mA C C C/W C/W C/W C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 5. LVPECL DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V 0C Symbol ICC VIH VIL VIHCMR Characteristic Core Power Supply Current Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 2) (Figure 4) LVPECL_CLK/LVPECL_CLK Input HIGH Current Input LOW Current Min 75 VCCI - 1.165 VCCI - 1.945 Typ 95 Max 115 VCCI - 0.88 VCCI - 1.6 Min 75 VCCI - 1.165 VCCI - 1.945 25C Typ 95 Max 115 VCCI - 0.88 VCCI - 1.6 Min 75 VCCI - 1.165 VCCI - 1.945 85C Typ 95 Max 115 VCCI - 0.88 VCCI - 1.6 Unit mA V V 1.2 -150 -150 VCCI 150 150 1.2 -150 -150 VCCI 150 150 1.2 -150 -150 VCCI 150 150 V mA mA IIH IIL NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. VIHCMR max varies 1:1 with VCCI. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 6. LVTTL/LVCMOS DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V 0C Symbol VIH VIL IIH IIL Characteristic Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current -150 -300 Min 2.0 0.8 150 300 -150 -300 Typ Max Min 2.0 0.8 150 300 -150 -300 25C Typ Max Min 2.0 0.8 150 300 85C Typ Max Unit V V mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. http://onsemi.com 4 MC100EP809 Table 7. LVTTL/LVCMOS DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V 0C Symbol VOH VOL VIH VIL VX IIH IIL VIHCMR Characteristic Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Input HIGH Voltage (Figure 5) Input LOW Voltage (Figure 5) HSTL Input Crossover Voltage Input HIGH Current Input LOW Current Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) HSTL_CLK/HSTL_CLK Min 1.0 0.1 VX + 0.1 -0.3 0.68 -150 -300 - Typ Max 1.2 0.4 1.6 VX - 0.1 0.9 150 300 Min 1.0 0.1 VX + 0.1 -0.3 0.68 -150 -300 - 25C Typ Max 1.2 0.4 1.6 VX - 0.1 0.9 150 300 Min 1.0 0.1 VX + 0.1 -0.3 0.68 -150 -300 - 85C Typ Max 1.2 0.4 1.6 VX - 0.1 0.9 150 300 Unit V V V V V mA mA 0.6 VCCI - 1.2 0.6 VCCI - 1.2 0.6 VCCI - 1.2 V V NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. All outputs loaded with 50 W to GND (Figure 6). 4. VIHCMR max varies 1:1 with VCCI. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 8. AC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V (Note 5) 0C Symbol VOpp Characteristic Differential Output Voltage fout < 100 MHz (Figure 3) fout < 500 MHz fout < 750 MHz Propagation Delay (Differential Configuration) LVPECL_CLK to Q HSTL_CLK to Q Within-Device Skew (Note 6) Device-to-Device Skew (Note 7) Random Clock Jitter (Figure 3) (RMS) Input Swing (Differential Configuration) (Note 8) (Figure 4) LVPECL HSTL OE Set Up Time (Note 9) OE Hold Time Output Rise/Fall Time (20% - 80%) 200 200 0.5 0.5 350 600 Min 600 600 450 680 690 Typ 850 750 575 800 830 15 100 1.4 930 990 50 200 3.0 200 200 0.5 0.5 350 450 600 Max Min 600 600 450 700 700 25C Typ 850 750 575 820 850 15 100 1.4 950 1000 50 200 3.0 200 200 0.5 0.5 350 600 Max Min 600 600 450 780 790 85C Typ 850 750 575 920 950 15 100 1.4 1070 1110 50 200 3.0 Max Unit mV mV ps ps ps ps ps mV mV ns ns ps tPLH tPHL tskew tJITTER VPP tS tH tr/tf NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Measured with 750 mV (LVPECL) source or 1 V (HSTL) source, 50% duty cycle clock source. All outputs loaded with 50 W to GND (Figure 6). 6. Skew is measured between outputs under identical transitions and conditions on any one device. 7. Device-to-Device skew for identical transitions and conditions. 8. VPP is the Differential Input Voltage swing required to maintain AC characteristics listed herein. 9. OE Set Up Time is defined with respect to the rising edge of the clock. OE High-to-Low transition ensures outputs remain disabled during the next clock cycle. OE Low-to-High transition enables normal operation of the next input clock (Figure 8). http://onsemi.com 5 MC100EP809 900 800 700 VOPP (mV) 600 500 400 300 200 100 0 0 100 200 300 400 500 600 700 800 900 RMS JITTER VOPP 9 8 7 tJITTER ps (RMS) 6 5 4 3 2 1 1000 FREQUENCY (MHz) Figure 3. Output Frequency (FOUT) versus Output Voltage (VOPP) and Random Clock Jitter (tJITTER) http://onsemi.com 6 MC100EP809 VCCI(LVPECL) VPP VIHCMR VIH(DIFF) VIL(DIFF) GND VPP VCCI VCCO(HSTL) VIH(DIFF) VX VIL(DIFF) GND Figure 4. LVPECL Differential Input Levels Figure 5. HSTL Differential Input Levels Q Z = 50 W HSTL OUTPUT Q 50 W 50 W GROUND Figure 6. HSTL Output Termination and AC Test Reference CLK/CLK D.C. Bias* *Must fall within 680 to 900 mV (Preferably (VIH + VIL)/2). Figure 7. HSTL Single-Ended Input Configuration CLK CLK OE Q Q Figure 8. Output Enable (OE) Timing Diagram http://onsemi.com 7 MC100EP809 ORDERING INFORMATION Device MC100EP809FA MC100EP809FAG MC100EP809FAR2 MC100EP809FAR2G Package LQFP-32 LQFP-32 (Pb-Free) LQFP-32 LQFP-32 (Pb-Free) Shipping 250 Units / Tray 250 Units / Tray 2000 / Tape & Reel 2000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices http://onsemi.com 8 MC100EP809 PACKAGE DIMENSIONS 32 LEAD LQFP CASE 873A-02 ISSUE C -T-, -U-, -Z- AE P V V1 DETAIL Y BASE METAL 32 A1 A 25 4X 0.20 (0.008) AB T-U Z 1 -T- B B1 8 -U- 17 9 S1 S 8X M_ R J G -AB- SEATING PLANE DETAIL AD CE SECTION AE-AE -AC- 0.10 (0.004) AC 0.250 (0.010) H W X DETAIL AD K Q_ GAUGE PLANE ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 9 MC100EP809/D 0.20 (0.008) 9 -Z- 0.20 (0.008) AC T-U Z F D M 4X EE EE EE EE N AC T-U Z DETAIL Y AE |
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